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Espressif Systems /ESP32-C6 /I2S0 /TX_CONF

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Interpret as TX_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_RESET)TX_RESET 0 (TX_FIFO_RESET)TX_FIFO_RESET 0 (TX_START)TX_START 0 (TX_SLAVE_MOD)TX_SLAVE_MOD 0 (TX_MONO)TX_MONO 0 (TX_CHAN_EQUAL)TX_CHAN_EQUAL 0 (TX_BIG_ENDIAN)TX_BIG_ENDIAN 0 (TX_UPDATE)TX_UPDATE 0 (TX_MONO_FST_VLD)TX_MONO_FST_VLD 0TX_PCM_CONF 0 (TX_PCM_BYPASS)TX_PCM_BYPASS 0 (TX_STOP_EN)TX_STOP_EN 0 (TX_LEFT_ALIGN)TX_LEFT_ALIGN 0 (TX_24_FILL_EN)TX_24_FILL_EN 0 (TX_WS_IDLE_POL)TX_WS_IDLE_POL 0 (TX_BIT_ORDER)TX_BIT_ORDER 0 (TX_TDM_EN)TX_TDM_EN 0 (TX_PDM_EN)TX_PDM_EN 0TX_CHAN_MOD 0 (SIG_LOOPBACK)SIG_LOOPBACK

Description

I2S TX configure register

Fields

TX_RESET

Set this bit to reset transmitter
TX_FIFO_RESET

Set this bit to reset Tx AFIFO
TX_START

Set this bit to start transmitting data
TX_SLAVE_MOD

Set this bit to enable slave transmitter mode
TX_MONO

Set this bit to enable transmitter in mono mode
TX_CHAN_EQUAL

1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
TX_BIG_ENDIAN

I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
TX_UPDATE

Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
TX_MONO_FST_VLD

1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
TX_PCM_CONF

I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
TX_PCM_BYPASS

Set this bit to bypass Compress/Decompress module for transmitted data.
TX_STOP_EN

Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
TX_LEFT_ALIGN

1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
TX_24_FILL_EN

1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
TX_WS_IDLE_POL

0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
TX_BIT_ORDER

I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
TX_TDM_EN

1: Enable I2S TDM Tx mode . 0: Disable.
TX_PDM_EN

1: Enable I2S PDM Tx mode . 0: Disable.
TX_CHAN_MOD

I2S transmitter channel mode configuration bits.
SIG_LOOPBACK

Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data